1. Field of the Invention
The invention relates to interconnecting nodes and information elements in electronic, computer, and communication systems (for example, cells on an integrated circuit, modules in a multiprocessor system, or subscribers to a telecommunications network). Because of the general character of the topology that is the foundation of the proposed method and of the resulting structure, it can be used in hardware as well as in software architecture design.
2. Description of Background Art
Optimizing node interconnections is very important for modern electronic, computer, and communication systems. One of the most effective and general architectures of nodes interconnections is based on a full graph diagram in which each node is connected to every other node. A straightforward implementation of this architecture, however, cannot be realized practically in devices because of the very large number of interconnecting lines between nodes.
Numerous attempts to solve both this problem and the problems of the number and the complexity of the switching elements, delay time, etc. were not successful. For example, the well known hypercube architecture diminishes the number of interconnecting lines, but increases the delay time of information exchanges.
The hypercube architecture has many other disadvantages. Particularly, k-dimensional hypercubes have N=2.sup.k vertices, so these structures are restricted to having exactly 2.sup.k nodes. Because structure sizes must be a power of 2, there are large gaps in the sizes of systems that can be built with the hypercubes. This severely restricts the number of possible nodes.
A hypercube architecture has a delay time approximately equal to 2 log N, and has a "skew", i.e., different delay times for different interconnecting nodes. This creates additional difficulties when using hypercube structures in system designs.
Similar problems are characteristic of other known methods of interconnection and corresponding types of architectures (bus, ring, etc.). Detailed descriptions of the interconnection structures mentioned above and their main characteristics can be found in H. Sullivan and T. Bashkov, "A large scale, homogenous, fully distributed parallel machine, 1." Proc. 4 Symp. Comp. Arch., 1977, pp. 105-117 and in T. L. Casavant, P. Tvrdik, F. Plasil, Parallel computers: theory and practice, IEEE Computer Society Press, Los Alamitos, Calif., 1995, 422 pp., the subject matter of both are incorporated herein by reference. Neither one of these architectures, however, can ensure an optimal solution to the interconnection problems.
Consequently, there is a need to develop an interconnecting method and structure that lacks the above-described shortcomings of known architectures.